1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory cell and a manufacturing process thereof having an improved pattern structure of an active region.
2. Discussion of the Related Art
Generally, a DRAM cell in a semiconductor memory device for performing data storage and read out operations is constructed as shown in the equivalent circuit diagram as in FIG. 1. According to FIG. 1 above, a memory cell 100 includes a transistor Q and a capacitor Cs. The gate of the transistor Q is connected to a word line 200, and one of either the source or drain electrode is connected to one terminal of the capacitor Cs while the other electrode is connected to a bit line 300.
The operation of a DRAM as constructed above is described below. First, in the case of a data storage operation, a specified voltage is applied to the word line 200, so that the transistor Q conducts. Next, charge on the bit line 300 is stored in the capacitor Cs and data is thus stored. When data is read out, a specified voltage is applied to the word line 200, so that the transistor Q conducts. Then, charge on the capacitor Cs is read out through the bit line 300.
The layout and structure of a conventional memory cell which operates on the general principles described above is described in reference to FIG. 2 and FIG. 3. FIG. 2 is a two-dimensional layout of a conventional memory Cell. FIG. 3 is a cross-sectional diagram along line III--III of FIG. 2.
A memory cell comprises a MOS transistor and capacitor formed on a silicon substrate 21. An n channel MOS transistor comprises a gate electrode 23 used as a word line and n+ impurity diffusion regions 24 and 25 used as drain and source regions. The n+ impurity diffusion regions 24 and 25 are formed a certain distance apart to limit the channel regions on the silicon substrate 21. The gate electrode 23 is formed on the channel region through a gate oxide layer 22. The capacitor is connected to the n+ impurity diffusion region 24 used as the drain region. The capacitor comprises a storage node 26 connected to the n+ impurity diffusion region 24, and a cell plate 28 formed through a capacitor dielectric layer 27 on the storage node 26. Also, a bit line 31 is connected to the source region 25 through a contact hole 30. In addition, an intermediate dielectric layer 29 is formed between the bit line 31, word line 23, and cell plate 28.
As in the structure above, a capacitor in a conventional memory cell is first formed on an active region, then a bit line is formed above the capacitor. The area of a capacitor thus formed is restricted by the bit line, so that the area the capacitor occupies in a high density integrated memory cell is further reduced. As the capacitor area is decreased, the data reading margin is also reduced, and the cell becomes unstable since data may not be read correctly. Accordingly, for a higher reading margin, it becomes desirable to increase the area of the capacitor occupied by the storage node 26, dielectric layer 27 and cell plate 28.
However, by employing this method, the difference of the capacitor among terminals becomes large, and the aspect ratio of the bit line contact hole 30 increases. Consequently, a void may form in the contact hole when a metal material is deposited for the bit line, thus reducing the cell performance. In addition, difficulties in the processes of contact filling and line patterning also make this method unsuitable for high density integration.
A DRAM cell with a stacked capacitor structure formed above the bit line to increase the area of capacitor has been proposed as described below.
FIG. 4 is a two-dimensional layout of a conventional memory cell with a stacked capacitor structure above the bit line. FIG. 5 is a cross-sectional diagram along line V--V of FIG. 4. According to FIGS. 4 and 5, a gate electrode 43 is formed above a gate oxide layer 42 on a silicon substrate 41 and is used as a word line. First and second impurity diffusion regions 44 and 45 are formed adjacent the gate electrodes 43 at regular intervals on the substrate 41 and are used as source/drain regions. A bit line 47 connects to the first impurity diffusion region 44. This bit line 47 is formed so that it passes over the word line 43. A first intermediate dielectric layer 46 is formed between the word line 43 and the bit line 47. A storage node 49 is formed through a second intermediate dielectric layer 48. The second intermediate dielectric layer 48 is formed above the bit line 47. The storage node 49 is in electrical contact with the second impurity diffusion region 45. A cell plate 51 is formed over a capacitor dielectric layer 50, which is positioned above the storage node 49. As shown in FIG. 4, the active region 52 is situated diagonally with regard to the bit line 47 and the word line 43.
In a structure as described above, the storage node 49 and cell plate 51 may be expanded at the contact region of the bit line 47 and the first impurity diffusion region 44. Consequently, the area of the capacitor is not limited by bit line 47, thus increasing the capacitance. However, since the active region 52 lies diagonally with regard to the bit line 47 and the word line 23, and the ends of the active region 52 take on a bent shape, the memory cell takes on a complicated layout pattern. Therefore, to form separating regions which isolate the plurality of active regions on the substrate, a diagonal pattern becomes necessary, making the manufacturing process more difficult. Also, there are more corners present when forming the pattern due to the diagonal active regions, leading to shrinkage and pattern variability from the proximity effect. Thus, the packing density becomes lower in such a diagonal active pattern. As a result, a memory cell with a conventional stacked capacitor structure above becomes unsuitable as a DRAM cell in a high density integration device.